New Challenge in 1.5 Mil Taiko Wafer with High Wafer Strength
Wafer thinning has been the most direct and effective process improvement in cutting power consumption and input impedance of power semiconductors which not only reduce packaging dimension but also extends the service life of wafers by lowering RDS (on) and heat accumulation.
However, the MOSFET foundries are facing a challenge of balancing thickness and strength of wafers to minimize the risks of soaring rate of broken wafers.
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ProPowertek has developed the thinning technology for wafers 2mil, 1.5mil, and even 10um thick. The silicon chips shown in Figure 1 are so thin that red light can penetrate the wafers when white light source on their backside.
Figure 1: From Scanning Electron Microscope (SEM) results, the X-SEM of 50um, 38um, and 10um thinned wafer
I. In Terms of Wafer Grinding
The surface damage layer by TEM analysis shows that the depth of the damage layer goes along with grinding level (Figure 2) which result in mechanic stress accumulation, poorer die strength and a more demanding packaging and testing process.
The ProPowert exclusively optimized process to take up this challenge and rise production yield (Figure 2).
TEM maps of damage layers in blanket, 2mil and 1.5 mil wafers
II. In Terms of Wafer Etching
Figure 3: Increase wafer strength through etching process to reduce stress accumulation (Data normalized).
Figure 4: Optimize the etching conditions to obtain higher strength and lower stress (HsLs) to facilitate following processing (Data normalized).
Mr. Hsieh / Felipe
Tel: +886-3-579-9209#5802
email: contact@propowertek.com