Tech Library

How to Quickly Reduce MOSFET RDS(on) Without Changing Your Design

MOSFET has been playing the role of “switch socket” for a long time in the electronics world. Featuring a high switching speed, low input impedance and low power consumption, it not only withstands high currents but also improves circuit conversion efficiency, and these factors combined made it a critical power component.

Pursuing high-efficiency power conversion and low power consumption, manufacturers found a shortcut: reducing RDS(on).

A quick glance on RDS(on)

RDS(on) is composed of several impedances: source contact impedance Rcs, N+ internal impedance Rn+, channel impedance Rchannel, accumulation zone impedance Ra, JFET region impedance RJFET, drift region impedance Rd, substrate impedance Rsub, drain contact impedance Rcd, and sum of package impedance Rpack.

I. Begin with Si process and design

This method has been widely adopted in the past 10 years. Recently, we have observed several MOSFETs with low RDS(on) from leading brands, including CoolMOS by Infineon based on the multi-layer epitaxial stack technology, the MDMesh by STMicroelectronics, DTMOS by Toshiba, and SuperMOS by Fairchild, which employ deep trench refill technology. OnSemi used this, along with a Liner oxide design, in its UltiMOS to reduce RDS(on) via a super junction with higher N-type Epi concentration without loss of depth in the depletion region. The CoolMOS by Infineon has been remarkably well accepted by the industry since its launch in 1998, and more than 1.6 billion pieces of it have been sold in last three years(Note1).

II. Improve its package

III. Try thinning the wafer

As mentioned earlier, RDS(on) is determined by the sum of a series of resistance sums. Part of it is subject to Rsub which, in turn, is related to the doping concentration and the thickness of the wafer itself. That is, thinning substrate may lower RDS(on). The “wafer thinning” technique has been adopted by the industry in recent years to make wafers thinned.

However, to make wafers of very precise, very thin thickness is quite challenging technology. First of all, it is quite difficult that thinning wafers to reach a certain thickness, as the edge of the wafer tend to warp when wafer being thinned. Warped wafers may result in difficulties in the subsequent processes as they are fragile during shipment or during manual handling (when auto-handling fails due to warpage). ProPowertek employs the Taiko technique to overcome this issue. By leaving a Taiko ring on wafer edge, similar to drum ring, leaving edge of wafer with partial precise grinding on wafer center, the wafer may come out without warpage. The process of thinning wafers to 50um and is now in mass production for multiple customers with line yields up to 99.5%

In addition, ProPowertek is able to obtain good wafer uniformity with total thickness variation (TTV) well controlled within 3um by applying simultaneous etching technology. We found that only thinning wafers from 100um to 50um can reduce RDS(on) 19% (Note2)in same testing condition and same device design without any design changes nor any modifications to processes in the foundry or backend packaging plant.

Caption: By thinning the wafer from 100um to 50um with our techniques, ProPowertek can help customers to lower power MOSFET RDS(on) around 19%.

Click this link or the image above to view the 15 um wafer thinning video: https://pse.is/Waferthintw